By Liesbet Van der Perre, Jan Craninckx, Antoine Dejonghe
The expanding desire for sensible flexibility (the variety of instant criteria is huge and anticipated to develop) and the exploding rate of system-on-chip layout will make implementation of instant criteria on reconfigurable radios the one conceivable alternative sooner or later. software program outlined Radios (SDRs) will supply greater flexibility at lower price. additionally, they're key enablers within the consciousness of cognitive radios, as a way to let extra effective use of community and spectral resources.
Green SDRs should be crucial, to avoid wasting on the most important and scarce assets: strength and spectrum. Green software program outlined Radios gives perception within the traits requesting eco-friendly SDRs. the basic parts of those radios are elaborated on. in particular, layout options and ways for energy-scalable SDRs, either for the radio front-end and the electronic baseband (including and software), are defined. clever (cross-layer) keep watch over is brought because the key to accomplish power effective operation and seamless connectivity. final yet now not least the publication makes a speciality of cognitive radios, beginning a brand new instant order. those radios construct on SDR structures, improved with a sensing engine and clever keep watch over.
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Extra resources for Green Software Defined Radios: Enabling seamless connectivity while saving on hardware and energy
The LNA has an ESD-protected input pad which employs two diodes. These are taken into account in the simulations. – The LNA is connected to the outside world by bonding wires. 2 nH inductor and included in simulations. 44 3 Software-Defined Radio Front-Ends – The cascode transistor used in the circuit shown in Fig. 8 is not used in the final implementation. The required high gain (22 dB) results in a large swing at the LNA output. The cascode limits the available headroom and is therefore left out.
The gate capacitance therefore drops considerably, although special attention should be given to the fact that for large signals the transistor can enter the accumulation mode, where the capacitance is again high . Simulations have shown here that the large-signal capacitance is hardly affected by the accumulation effect. • Third, the switch transistors (SW1–SW2) also turn off and only the drain parasitics stay attached to the gate, which results in a large drop is capacitance. To summarize, we see that the NMOS capacitance stays fixed, the PMOS reduces, and the switch disappears almost completely.
The VCO can then be switched to the next tuning curve (as determined during the power-up calibration routine), and the data in the look-up data must be updated. 5 Implementation Results The VCO has been implemented in the SDR prototype, together with a fractional-N PLL. It is a traditional fourth order, type-2 charge-pump PLL with active loop filter and a MASH or cascaded 1-1-1 sigma-delta modulator. The external reference clock is 40 MHz. The active loop filter has a total capacitance of 190 pF, an amount that is low enough to be integrated on chip.